Patent Number: 6,251,747

Title: Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices

Abstract: A method of forming a semiconductor device minimizes oxide recessing in a trench of a semiconductor device. In one embodiment, forming a nitride spacer surrounding the top trench corner oxide in a shallow trench isolation region protects the corner oxide from being etched during processing. Oxide recessing in the trench is undesirable since it results in high electric fields around the sharp top corners of the trenches and V.sub.t roll-off of the transistors. According to one example embodiment, STI regions filled with an HDP oxide and having undergone planarization, are masked. The masking substantially covers the HDP oxide and overlaps at least portions of nitride regions. Unmasked areas of the nitride regions are etched away forming nitride spacers on both sides of the HDP oxide fill.

Inventors: Zheng; Tammy (Fremont, CA), Nouri; Faran (Los Altos, CA)

Assignee: Philips Semiconductors, Inc.

International Classification: H01L 21/762 (20060101); H01L 21/70 (20060101); H01L 21/8234 (20060101); H01L 021/76 ()

Expiration Date: 06/26/2018