Patent Number: 6,251,748

Title: Method of manufacturing shallow trench isolation structure

Abstract: A method of manufacturing shallow trench isolation structure comprising the steps of forming a polysilicon mask layer over a substrate, and then patterning the polysilicon mask layer and the substrate to form a trench. Thereafter, a silicon nitride layer is formed covering the sidewalls of the trench. Next, a high-density chemical vapor deposition method is used to deposit oxide material into the trench. Finally, the surface is polished to remove a portion of the oxide layer and the silicon nitride layer until the polysilicon mask layer is exposed. The shallow trench isolation structure can avoid subthreshold kink effect and reduce subthreshold leakage current.

Inventors: Tsai; Meng-Jin (Kaohsiung, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/762 (20060101); H01L 21/70 (20060101); H01L 021/76 ()

Expiration Date: 06/26/2018