Patent Number: 6,251,750

Title: Method for manufacturing shallow trench isolation

Abstract: A method of manufacturing a shallow trench isolation in a substrate. The substrate has a pad oxide layer and a mask layer formed thereon in sequence and a trench penetrating through the mask layer and the pad oxide layer and into the substrate. A thermal oxidation process is performed to form a liner oxide layer on a portion of the substrate exposed by the trench. A spacer is formed on the sidewall of the mask layer, the pad oxide layer and the trench. An oxidation process is performed to oxidize a portion of the substrate under a portion of the liner oxide layer located on the bottom of the trench. An insulating layer is formed over the substrate and filling the trench. A planarization process is performed to remove a portion of the insulating layer until the mask layer is exposed. The mask layer and the pad oxide layer are removed.

Inventors: Lee; Claymens (Kaohsiung Hsien, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/762 (20060101); H01L 21/70 (20060101); H01L 021/76 ()

Expiration Date: 06/26/2018