Patent Number: 6,251,761

Title: Process for polycrystalline silicon gates and high-K dielectric compatibility

Abstract: A gate stack (104) including a gate dielectric with reduced effective electrical thickness. A high-k dielectric (108) is formed over the silicon substrate (102). Remote plasma nitridation of the high-k dielectric is performed to create a nitride layer (107) over the high-k dielectric (107). A conductive layer (110) is formed over the nitride layer (107) forming the gate electrode.

Inventors: Rodder; Mark S. (University Park, TX), Hattangady; Sunil V. (McKinney, TX)

Assignee: Texas Instruments Incorporated

International Classification: H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 29/51 (20060101); H01L 29/40 (20060101); H01L 021/320 (); H01L 021/476 (); H01L 021/823 (); H01L 021/336 ()

Expiration Date: 06/26/2018