Patent Number: 6,251,762

Title: Method and device for improved salicide resistance on polysilicon gates

Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 .mu.M. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

Inventors: Jan; Chia-Hong (Portland, OR), Tsai; Julie A. (Beaverton, OR), Yang; Simon (Portland, OR), Ghani; Tahir (Beaverton, OR), Whitehill; Kevin A. (Portland, OR), Keating; Steven J. (Beaverton, OR), Myers; Alan (Portland, OR)

Assignee: Intel Corporation

International Classification: H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 021/320 (); H01L 021/476 ()

Expiration Date: 06/26/2018