Patent Number: 6,251,773

Title: Method of designing and structure for visual and electrical test of semiconductor devices

Abstract: In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.

Inventors: Hartswick; Thomas J. (Underhill, VT), Masters; Mark E. (Essex Junction, VT)

Assignee: International Business Machines Corporation

International Classification: H01L 23/52 (20060101); H01L 23/58 (20060101); H01L 23/522 (20060101); H01L 021/476 ()

Expiration Date: 06/26/2018