Patent Number: 6,251,774

Title: Method of manufacturing a semiconductor device

Abstract: There is described a method of manufacturing a semiconductor device for the purpose of preventing damage to a lower wiring layer, wherein wiring elements of dual damascene structure are formed on the lower wiring layer. Under the method, a first silicon nitride film, a first silicon oxide film, a second silicon nitride film, and a second silicon oxide film are formed, in this sequence, on a lower wiring layer. A via hole is formed at a position above the lower wiring layer so as to pass through the second silicon oxide film and the second silicon nitride film. A photoresist is embedded into the via hole so as to cover the internal wall surface thereof. After formation of a protective film from the photoresist, predetermined portions of the second silicon oxide film and the second silicon nitride film are removed, thus forming a wiring trench.

Inventors: Harada; Akihiko (Tokyo, JP), Saito; Takayuki (Tokyo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 21/314 (20060101); H01L 021/314 (); H01L 021/476 ()

Expiration Date: 06/26/2018