Patent Number: 6,251,778

Title: Method for using CMP process in a salicide process

Abstract: A method for using CMP processes in the salicide process for preventing bridging. Beginning with a semiconductor substrate with active regions defined completely by field oxide, the following steps are perfromed: forming a gate electrode and spaced lightly doped source and drain regions, the gate electrode comprising a gate oxide layer and a conducting gate; forming a hard mask layer on the gate electrode; forming spacers on sidewalls of the hard mask layer and the gate electrode, wherein the material used for the spacers is different from the material used for the hard mask layer; implanting ions into the substrate to form highly doped source and drain regions; removing the hard mask layer such that an opening is formed; conformally forming a metal layer on the source and drain regions, the spacers, and the conducting gate; forming an insulating layer on the metal layer and filling the opening, wherein the material of the insulating layer is different from the material of the spacers; polishing to remove an upper portion of the insulating layer, the metal layer and the spacers, whereby the metal layer becomes discontinuous; removing a portion of the metal layer between the spacers and the insulating layer; removing the insulating layer; and converting the metal layer to a silicide layer.

Inventors: Fang; Edberg (Yunlin Hsien, TW), Tsai; T. C. (Hsinchu, TW), Liu; L. M. (Hsinchu, TW)

Assignee: United Microelectronics Corporation

International Classification: H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 21/70 (20060101); H01L 21/285 (20060101); H01L 21/768 (20060101); H01L 021/44 ()

Expiration Date: 06/26/2018