Patent Number: 6,251,781

Title: Method to deposit a platinum seed layer for use in selective copper plating

Abstract: A method of fabricating single and dual damascene copper interconnects is achieved. A semiconductor substrate layer is provided. Conductive traces are provided in an isolating dielectric layer. An intermetal dielectric layer is deposited overlying the conductive traces and the isolating dielectric layer. The intermetal dielectric layer is patterned to form trenches to expose the top surfaces of the underlying conductive traces. A barrier layer is deposited overlying the intermetal dielectric layer, the exposed conductive traces, and within the trenches. A platinum ionic seed solution is coated inside the trenches and overlying the barrier layer. A platinum seed layer is deposited from the ionic seed solution by exposing the platinum ionic seed solution to ultraviolet light. A copper layer is deposited by electroless plating to form copper interconnects, where the copper layer is only deposited overlying the platinum seed layer in the trenches, and where the deposition stops before the copper layer fills the trenches. The exposed barrier layer is polished down to the top surface of the intermetal dielectric layer. An encapsulation layer is deposited overlying the copper interconnects and the intermetal dielectric layer to complete the fabrication of the integrated circuit device.

Inventors: Zhou; Mei Sheng (Singapore, SG), Xu; Guo-Qin (Singapore, SG), Chan; Lap (San Francisco, CA)

Assignee: Chartered Semiconductor Manufacturing Ltd.

International Classification: H01L 23/52 (20060101); H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 23/532 (20060101); H01L 021/44 ()

Expiration Date: 06/26/2018