Patent Number: 6,251,783

Title: Method of manufacturing shallow trench isolation

Abstract: A method of manufacturing shallow trench isolation structures. The method includes the steps of depositing insulating material into the trench of a substrate to form an insulation layer. The substrate has a plurality of active regions, each occupying a different area and having different sizes. In addition, there is a silicon nitride layer on top of each active region. Thereafter, a photoresist layer is then deposited over the insulation layer. Next, a portion of the photoresist layer is etched back to expose a portion of the oxide layer so that the remaining photoresist material forms a cap layer over the recessed area of the insulation layer. Subsequently, using the photoresist cap layer as a mask, the insulation layer is etched to remove a portion of the exposed oxide layer, thereby forming trenches within the oxide layer. After that, the photoresist cap layer is removed. Finally, a chemical-mechanical polishing operation is carried out to polish the insulation layer until the silicon nitride layer is exposed.

Inventors: Yew; Tri-Rung (Hsien, TW), Huang; Kuo-Tai (Hsinchu, TW), Yang; Gwo-Shii (Hsinchu, TW), Lur; Water (Taipei, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/762 (20060101); H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/3105 (20060101); H01L 021/302 ()

Expiration Date: 06/26/2018