Patent Number: 6,251,788

Title: Method of integrated circuit polishing without dishing effects

Abstract: A method for planarizing the surface of a semiconductor wafer is disclosed. It involves the steps of: (a) applying a coating solution containing a polymeric material on the dielectric film; (b) curing the polymeric material to cause the polymeric material to become hardened and form a polymeric layer; (c) subjecting the polymeric layer to a gas plasma treatment, so that at least a portion of the polymeric layer becomes a SiO.sub.2 -like layer which can be polished by a conventional oxide-type CMP slurry; (d) depositing a PETEOS film on the SiO.sub.2 -like layer; and (f) CMP polishing the PETEOS film and the SiO.sub.2 -like laye using a conventional oxide-type CMP slurry. This method is particularly advantageous for fabricating semiconductor devices with relatively wide trenches wherein the polymer layer would warp into the bottom of the trench thus will not serve as an effective self-provided etch stop.

Inventors: Liou; Ping (Hsinchu, TW)

Assignee: Winbond Electronics Corp.

International Classification: H01L 21/02 (20060101); H01L 21/3105 (20060101); H01L 021/304 ()

Expiration Date: 06/26/2018