Patent Number: 6,251,799

Title: Method to provide low dielectric constant voids between adjacent conducting lines in a semiconductor device

Abstract: A method to provide low dielectric constant voids between adjacent conducting lines in a semiconductor device. Narrowly spaced metal lines are formed on the substrate surface. A dielectric layer is deposited overlying the metal lines and the substrate surface. A high water content, water saturated, environment is created for the spin-on-glass process. A pseudo-water condition exists on the surface of the dielectric layer prior to the deposition of the spin-on-glass layer. The spin-on-glass layer is deposited overlying the dielectric layer. Voids form in the spin-on-glass layer between the narrowly spaced metal lines. The spin-on-glass layer is baked. The integrated circuit device is completed.

Inventors: Lai; Wei-Sheng (Chu-Pei, TW), Chang; Yu-Ching (Hsin-Chu, TW), Ge; Chun-Hu (Hsin-Dien, TW), Chen; Chih-Ming (Yam Mei, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 021/31 ()

Expiration Date: 06/26/2018