Patent Number: 6,251,800

Title: Ultrathin deposited gate dielectric formation using low-power, low-pressure PECVD for improved semiconductor device performance

Abstract: An ultrathin gate dielectric and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A low-power, low-pressure plasma-enhanced chemical vapor deposition (PECVD) method employing silane and nitrous oxide sources is used to deposit the dielectric. As compared to conventional PECVD deposition, the method uses lower silane and nitrous oxide flow rates, a more dilute silane in nitrogen mixture, a lower chamber pressure, and a lower radio frequency power density. These settings allow plasma conditions to stabilize so that deposition may be performed in time increments at least as short as 0.1 second, so that oxide thicknesses at least as small as one angstrom may be controllably deposited. The oxide is preferably deposited in portions at multiple substrate mounting positions in a deposition chamber. Combination of oxide portions in this manner is believed to reduce the density of pinholes in the oxide, and the low-power, low-pressure deposition conditions are further believed to reduce plasma damage to the oxide and reduce the density of trap states in the oxide. A rapid thermal anneal of the oxide may be performed after deposition, and may improve the quality of the interface between the oxide and the underlying semiconductor substrate.

Inventors: Sun; Sey-Ping (Austin, TX), Gardner; Mark I. (Cedar Creek, TX), May; Charles E. (Gresham, OR)

Assignee: Advanced Micro Devices, Inc.

International Classification: C23C 16/40 (20060101); H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 21/316 (20060101); H01L 021/31 (); H01L 021/469 ()

Expiration Date: 06/26/2018