Patent Number: 6,253,250

Title: Method and apparatus for bridging a plurality of buses and handling of an exception event to provide bus isolation

Abstract: A bus bridge coupled between two bridges providing bus exception event isolation and address/data translation. In one embodiment the bus bridge includes two direct memory access (DMA) engines and a first-in-first-out (FIFO) buffer interface between the DMA engines to provide the bus exception isolation. The DMA engines and FIFOs also enable a packet based message passing architecture, which eliminates the need for address translation and also handles data reordering.

Inventors: Evans; Keith M. (San Jose, CA), Grundy; Kevin P. (Fremont, CA)

Assignee: Telocity, Incorporated

International Classification: G06F 15/173 (20060101); G06F 15/16 (20060101); G06F 015/16 (); G06F 015/173 ()

Expiration Date: 06/26/2018