Patent Number: 6,253,263

Title: System with logic gates having a progressive number of inputs connected to a first connection matrix receiving signals to be arbitrated from peripheral devices

Abstract: A peripheral device connecting system with priority arbitration includes a connection matrix connected to a plurality of peripheral devices capable of transmitting a signal to be arbitrated, e.g., an interrupt enable signal. The connection matrix includes first and second connection matrices connected to each other through a plurality of logic gates having a progressive number of inputs for transmitting in parallel a plurality of signals to be arbitrated. A connection matrix for a microcontroller-emulating chip includes a peripheral device connecting system with priority arbitration.

Inventors: Losi; Marco (Milan, IT), Pelagalli; Sergio (Milan, IT)

Assignee: STMicroelectronics S.r.l.

International Classification: G06F 13/20 (20060101); G06F 13/24 (20060101); G06F 013/26 ()

Expiration Date: 06/26/2018