Patent Number: 6,253,275

Title: Interrupt gating method for PCI bridges

Abstract: A method and apparatus for managing interrupt requests from devices on a subordinate bus is disclosed. An interrupt request storage area is provided on the bridge device to allow the bridge device to log and track interrupt requests. Once an interrupt request from an interrupting device is logged, all previous transactions from the interrupting device is allowed to complete while no further transactions from the interrupting device is allowed. All other devices operates normally during this time. Once the interrupt request is serviced, the interrupting device is allowed to resume normal operation. By providing a storage area to store the interrupt requests from devices on a subordinate bus, the unprocessed transactions in the bridge device and transactions from all other devices can be processed in an orderly manner.

Inventors: Waldron; Scott (Belmont, CA), Wong; Jacques Ah Miow (Santa Clara, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: G06F 13/40 (20060101); G06F 13/20 (20060101); G06F 13/24 (20060101); G06F 013/24 ()

Expiration Date: 06/26/2018