Patent Number: 6,253,276

Title: Apparatus for adaptive decoding of memory addresses

Abstract: One embodiment of the present invention provides an apparatus for accessing a computer memory that bypasses decoding delays for memory type information within a memory controller. This apparatus includes a decoding circuit, for decoding a current address received from a processor to produce characteristics of a current memory module that is being accessed by the current address. These characteristics may include the size, type and speed of modules in the computer memory. The apparatus also includes a control signal generation circuit, for generating signals to control a memory access to the current address based upon the characteristics of the current memory module. The apparatus further includes a comparison module for determining whether the current address falls within a previously accessed memory module. The apparatus additionally includes a bypassing circuit. If the comparison module indicates that the current address falls within the previously accessed memory module, this bypassing circuit causes characteristics of a previously accessed memory module, obtained from a prior decoding of a previous address, to be used to generate the control signals for controlling the memory access. In a variation on this embodiment, if the comparison module indicates that the current address falls outside the previously accessed memory module, the bypassing circuit is causes characteristics of a memory module accessed by the current address to be used to generate the control signals.

Inventors: Jeddeloh; Joseph M. (Minneapolis, MN)

Assignee: Micron Technology, Inc.

International Classification: G06F 12/02 (20060101); G06F 012/06 ()

Expiration Date: 06/26/2018