Patent Number: 6,253,277

Title: Memory system having flexible addressing and method using tag and data bus communication

Abstract: A non-volatile memory system having a memory controller, an array of memory cells and a memory operation manager. The operation manager carries out memory program, read and erase operation upon receipt of program, read and erase instruction from the controller, typically over a system bus. The address block circuitry is provided in the manager which is capable of performing an memory operation on a single address or on multiple addresses depending upon the state of the address block circuitry as determined by the controller. Multiple addresses can be generated based upon a single address provided by the controller so that sectors of the memory can be programmed or read thereby simplifying memory operations and reducing the overhead of the memory controller.

Inventors: Lakhani; Vinod C. (Milpitas, CA), Norman; Robert D. (San Jose, CA), Chevallier; Christophe J. (Palo Alto, CA)

Assignee: Micron Technology, Inc.

International Classification: G06F 12/06 (20060101); G06F 012/00 ()

Expiration Date: 06/26/2018