Patent Number: 6,253,278

Title: Synchronous DRAM modules including multiple clock out signals for increasing processing speed

Abstract: Additional clock-outs are included on DRAMs in a multiple Dual In-Line Module Memory (DIMM) system having DRAMs of different data widths. The additional clock-outs balance the loads seen by the DRAM clock-out and data-out, thereby reducing signal skew between the DRAM data and clock lines. Additionally, in a second embodiment, every other clock line in a series of DRAMs comprising a DIMM are left unconnected. The data from the non connected DRAMs is clocked using the clock line of its neighbor.

Inventors: Ryan; Kevin J. (Eagle, ID)

Assignee: Micron Technology, Inc.

International Classification: G06F 13/16 (20060101); G11C 7/10 (20060101); G11C 5/00 (20060101); G06F 012/00 (); G06F 013/00 ()

Expiration Date: 06/26/2018