Patent Number: 6,253,286

Title: Apparatus for adjusting a store instruction having memory hierarchy control bits

Abstract: An apparatus for adjusting a STORE instruction having memory hierarchy control bits is disclosed. A multiprocessor data processing system includes a multi-level memory hierarchy. The apparatus for adjusting control bits within an instruction to be utilized within the multi-level memory hierarchy comprises a performance monitor and a bit adjuster. The memory hierarchy control bits indicates a memory level within the multi-level memory hierarchy to which an updating operation should be applied. In response to the outputs from the performance monitor, the bit adjuster alters at least one of the memory hierarchy control bits within the instruction in order to achieve optimal performance for the updating operation.

Inventors: Arimilli; Ravi Kumar (Austin, TX), Dodson; John Steve (Pflugerville, TX), Guthrie; Guy Lynn (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 11/34 (20060101); G06F 12/08 (20060101); G06F 9/38 (20060101); G06F 9/312 (20060101); G06F 013/14 (); G06F 015/18 (); G05B 013/02 ()

Expiration Date: 06/26/2018