Patent Number: 6,253,288

Title: Hybrid cache/SIRO buffer system

Abstract: A hybrid cache/SIRO buffer system includes a latch array for storing data words corresponding to system addresses; read command generator circuitry for launching data read commands to a memory system; a write pointer; write circuitry for storing data arriving from the memory system into the latch array at the location indicated by the write pointer; lowest and highest pointers for indicating the locations in the latch array corresponding to a lowest and a highest system address for which a read command has been launched; read circuitry for retrieving data from the latch array randomly; and control circuitry. Responsive to a first read request by a host system, the system begins retrieving data from memory beginning with an address equal to or close to the address associated with the first read request; then it speculatively reads ahead. As read requests from the host system continue to be processed by the system, more speculative reads are executed until the buffer is nearly full of data. Once near-fullness occurs, low-address data in the buffer are overwritten with new data. In this manner, a traveling window to memory is provided. If the host system begins requesting data from an address region not covered by the window and such out-of-window requests result in a threshold number of buffer "misses," then the system reinitializes itself. Upon reinitialization, the system effectively opens a new memory window corresponding to the new range of addresses being requested by the host system.

Inventors: McAllister; David L. (Fort Collins, CO), Diehl; Michael R. (Loveland, CO)

Assignee: Hewlett-Packard Company

International Classification: G06F 12/08 (20060101); G06F 012/00 ()

Expiration Date: 06/26/2018