Patent Number: 6,253,290

Title: Multiprocessor system capable of circumventing write monitoring of cache memories

Abstract: A multiprocessor system having a plurality of processor units each including a CPU and a local cache memory connected to the CPU. The CPUs have their shared bus terminals connected to a global shared bus, and the local cache memories have their bus terminals connected to a global unshared bus. The global shared bus is connected to an external shared memory for storing shared information used in common by the CPUs, and the global unshared bus is connected to an external unshared memory for storing unshared information used by the CPUs. This configuration can solve a problem of a conventional multiprocessor system in that it takes a rather long time for a cache memory to monitor write operations of the other cache memories, its processing speed is reduced because write back caches cannot be used, and its cost is increased because inexpensive caches cannot be used.

Inventors: Nakamoto; Yukio (Tokyo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G06F 12/08 (20060101); G06F 012/00 ()

Expiration Date: 06/26/2018