Patent Number: 6,253,291

Title: Method and apparatus for relaxing the FIFO ordering constraint for memory accesses in a multi-processor asynchronous cache system

Abstract: According to the present invention, each processor in a multi-processor system separates locally generated processor requests and remote processor requests from the snoop queue into two categories. In the first category, are all coherence transactions, both read and write, generated by the local processor, as well as all coherence transactions generated by a remote processor which are write accesses. Each of the transactions in the first category maintain a strict FIFO structure wherein accesses to the cache are performed and retired. In the second category are all coherence transactions generated by a remote processor which are read accesses. In the second category of transactions, there are no order constraints between the transactions, with the exception that a transaction in the second category which references the same memory location as a transaction in the first category cannot be performed, if the transaction in the first category that was received before the transaction in the second category, and has not yet been completed. During this exception, the FIFO order must be maintained between the transaction in the first category and the transaction in the second category.

Inventors: Pong; Fong (Mountain View, CA), Hetherington; Rick C. (Pleasanton, CA)

Assignee: Sun Microsystems, Inc.

International Classification: G06F 12/08 (20060101); G06F 012/00 ()

Expiration Date: 06/26/2018