Patent Number: 6,253,297

Title: Memory control using memory state information for reducing access latency

Abstract: A memory controller circuit (18a) for coupling to a memory (24), where the memory has a plurality of rows. The memory controller circuit includes circuitry (28) for receiving signals representative of requests to access the memory. Given these signals, a first such signal representative of a first request to access the memory is received by the circuitry for receiving and comprises a first address in the memory, and a second signal representative of a second request to access the memory is received by the circuitry for receiving after the first signal and comprises a second address in the memory. The memory controller circuit also includes determining circuitry (30, RAn, AC.sub.13 Bn.sub.13 ROW, C_B_Rn) for determining whether the second address is directed to a same one of the plurality of rows as the first address. Still further, the memory controller circuit includes circuitry (30) for issuing control signals to the memory in response to receiving signals representative of requests to access the memory. These control signals cause a first memory access to occur in response to the first request and a second memory access to occur in response to the second request. Lastly, in response to the determining circuitry determining that the second address is directed to the same one of the plurality of rows as the first address, the circuitry for issuing control signals issues control signals to the memory such that the same one of the plurality of rows is maintained active between the first and second access.

Inventors: Chauvel; Gerard (Antibes, FR), Lasserre; Serge (Frejus, FR), d'Inverno; Dominique Benoit Jacques (Villeneuve-Loubet, FR)

Assignee: Texas Instruments Incorporated

International Classification: G06F 12/00 (20060101); G06F 13/30 (20060101); G06F 13/20 (20060101); G06F 012/00 ()

Expiration Date: 06/26/2018