Patent Number: 6,253,298

Title: Synchronous SRAM having pipelined enable

Abstract: A synchronous burst SRAM device comprising an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean function of the chip enable signals; an enable register having an input connected to the chip enable and select logic for temporarily storing the SRAM core enable signal, and having an output; a pipelined enable register coupled between the enable register and the SRAM core for temporarily storing the SRAM core enable signal and delaying propagation of the core enable signal to the SRAM core; and pipelining logic coupled to at least one of the three chip enable inputs to permit pipelining operation of the synchronous burst SRAM device.

Inventors: Pawlowski; J. Thomas (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: D21G 9/00 (20060101); D21F 3/02 (20060101); D21F 3/04 (20060101); G11C 7/10 (20060101); G11C 11/419 (20060101); G06F 009/38 ()

Expiration Date: 06/26/2018