Patent Number: 6,253,308

Title: Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word

Abstract: A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Inventors: Kawasaki; Shumpei (Tokyo, JP), Sakakibara; Eiji (Kodaira, JP), Fukada; Kaoru (Koganei, JP), Yamazaki; Takanaga (Kodaira, JP), Akao; Yasushi (Kokubunji, JP), Baba; Shiro (Kokubunji, JP), Kihara; Toshimasa (Tachikawa, JP), Kurakazu; Keiichi (Tachikawa, JP), Tsukamoto; Takashi (Kodaira, JP), Masumura; Shigeki (Kodaira, JP), Tawara; Yasuhiro (Kodaira, JP), Kashiwagi; Yugo (Koganei, JP), Fujita; Shuya (Kodaira, JP), Ishida; Katsuhiko (Koganei, JP), Sawa; Noriko (Tama, JP), Asano; Yoichi (Tokyo, JP), Chaki; Hideaki (Tokorozawa, JP), Sugawara; Tadahiko (Kodaira, JP), Kainaga; Masahiro (Yokohama, JP), Noguchi; Kouki (Kokubunji, JP), Watabe; Mitsuru (Naka-gun, JP)

Assignee: Hitachi, Ltd.

International Classification: G06F 9/302 (20060101); G06F 9/32 (20060101); G06F 9/30 (20060101); G06F 9/38 (20060101); G06F 7/48 (20060101); G06F 9/318 (20060101); G06F 7/52 (20060101); G06F 015/00 ()

Expiration Date: 06/26/2018