Patent Number: 6,253,310

Title: Delayed deallocation of an arithmetic flags register

Abstract: A microprocessor capable of delaying the deallocation of an arithmetic flags register is described. A system processes instructions of a first instruction set architecture which has an arithmetic flags register. The system also processes instructions of a second instruction set architecture which is not compatible with the first instruction set architecture. In order to process a first instruction of the first instruction set architecture that implicitly updates the arithmetic flags register, the arithmetic flags register shares a physical destination register with a general register containing a result for the first instruction. An instruction that does not update the arithmetic flags but would deallocate the register containing the arithmetic flags triggers the delayed deallocation mechanism of the present invention.

Inventors: Ramirez; Ricardo (Cupertino, CA), Morrison; Mike (Santa Clara, CA)

Assignee: Intel Corporation

International Classification: G06F 9/32 (20060101); G06F 9/30 (20060101); G06F 9/318 (20060101); G06F 015/00 (); G06F 009/38 ()

Expiration Date: 06/26/2018