Patent Number: 6,253,312

Title: Method and apparatus for double operand load

Abstract: An apparatus and method are provided for concurrently loading single-precision operands into registers in a microprocessor floating point register file. The apparatus includes translation logic, data logic, and write back logic. The translation logic receives a load macro instruction prescribing an address, and decodes the load macro instruction into a double load micro instruction. The double load micro instruction directs the microprocessor to retrieve the two single-precision operands from the address and to load the two single-precision operands into the two floating point registers. The data logic, coupled to the translation logic, executes the double load micro instruction and retrieves the two single-precision operands from the address. The write back logic, coupled to the data logic, loads the two single-precision operands into the two floating point registers during a single write cycle.

Inventors: Elliott; Timothy A. (Austin, TX), Henry; G. Glenn (Austin, TX), Parks; Terry (Austin, TX)

Assignee: IP First, L.L.C.

International Classification: G06F 9/38 (20060101); G06F 9/312 (20060101); G06F 015/00 ()

Expiration Date: 06/26/2018