Patent Number: 6,253,314

Title: Instruction set and executing method of the same by microcomputer

Abstract: A computer program product, method and apparatus for utilizing common prefix codes in computing instructions so as to reduce the number instructions required to perform identical operations for varying operand sizes. In one form, the common prefix code is appended as the higher order portion of the instruction word to form a second series of instructions. These computing instructions may be utilized in conjunction with a flag register, which, in one application, designates which series of instructions to use; either the original instructions or the modified instructions containing the common prefix. In another application, the flag register designates which register or memory should be used to store the operands and the associated results. Through the use of common prefix codes and the flag register, operands of various sizes can be efficiently manipulated through a simplified scheme of instructions.

Inventors: Itoh; Sakae (Hyogo, JP)

Assignee: Mitsubishi Denki Kabushiki Kaisha

International Classification: G06F 9/318 (20060101); G06F 009/306 ()

Expiration Date: 06/26/2018