Patent Number: 6,253,316

Title: Three state branch history using one bit in a branch prediction mechanism

Abstract: A branch prediction unit stores a set of branch prediction history bits and branch selectors corresponding to each of a group of contiguous instruction bytes stored in an instruction cache. While only one bit is used to represent branch prediction history, three distinct states are represented in conjunction with the absence of a branch prediction. This provides for the storage of fewer bits, while maintaining a high degree of branch prediction accuracy. Each branch selector identifies the branch prediction to be selected if a fetch address corresponding to that branch selector is presented. In order to minimize the number of branch selectors stored for a group of contiguous instruction bytes, the group is divided into multiple byte ranges. The largest byte range may include a number of bytes comprising the shortest branch instruction in the instruction set (exclusive of the return instruction). For example, the shortest branch instruction may be two bytes in one embodiment. Therefore, the largest byte range is two bytes in the example. Since the branch selectors as a group change value (i.e. indicate a different branch instruction) only at the end byte of a predicted-taken branch instruction, fewer branch selectors may be stored than the number of bytes within the group.

Inventors: Tran; Thang M. (Austin, TX), McBride; Andrew (Austin, TX), Muthusamy; Karthikeyan (Austin, TX)

Assignee: Advanced Micro Devices, Inc.

International Classification: G06F 9/38 (20060101); G06F 009/44 (); G06F 009/42 (); G06F 009/32 ()

Expiration Date: 06/26/2018