Patent Number: 6,253,332

Title: Apparatus for generating shifted down clock signals

Abstract: An apparatus for reducing the magnitude of an external clock signal is provided wherein the external clock signal is provided on the motherboard of a computer, the signal is provided onto a plug-in CCA, and the signal must pass through a resistive voltage divider prior to being provided to circuits requiring the reduced magnitude signal.

Inventors: Hassan; Kazi M. (Sunnyvale, CA)

Assignee: Sun Microsystems

International Classification: G06F 1/10 (20060101); G06F 001/04 ()

Expiration Date: 06/26/2018