Patent Number: 6,253,343

Title: Method of design for testability test sequence generation method and semiconductor integrated circuit

Abstract: Flip-flops (FFs) to replace with scan FFs are selected for an integrated circuit designed at the gate level in order that the integrated circuit has an n-fold line-up structure. All FFs in an integrated circuit are temporarily selected as FFs to replace with scan FFs. Each FF to replace with a scan FF is temporarily selected as a FF to replace with a non-scan flip-flop, and the structure of the integrated circuit is checked if it has an n-folded line-up structure and if so, then the FF is selected as a FF to replace with a non-scan flip-flop. For an integrated circuit designed at the gate level, flip-flops to replace with scan flip-flops are selected in order that the integrated circuit has an n-fold line-up structure, without recognizing load/hold FFs as self-loop structure FF. Thereafter, FFs to replace with scan FFs are selected in such a way as to facilitate testing on load/hold FFs. The present invention guarantees high fault efficiency in identifying FFs to replace with scan FFs and achieves a higher compaction rate than conventional technology.

Inventors: Hosokawa; Toshinori (Osaka, JP), Ohta; Mitsuyasu (Osaka, JP)

Assignee: Matsushita Electric Industrial Co., Ltd.

International Classification: G01R 31/3183 (20060101); G01R 31/28 (20060101); G01R 31/3185 (20060101); G01R 031/28 ()

Expiration Date: 06/26/2018