Patent Number: 6,253,350

Title: Method and system for detecting errors within complementary logic circuits

Abstract: A method and system for detecting faults within dual-rail complementary logic circuits. A method and system are disclosed for detecting faults within dual-rail complementary logic circuits. A dual-rail complementary logic circuit is coupled to an associated complementary fault detection circuit within an integrated circuit. Thereafter, the presence of a non-complementary logic signal can be detected at an output of the complementary fault detection circuit, in response to providing an input signal at an input of the dual-rail complementary logic circuit, such that the presence of a non-complementary logic signal at an output of the complementary fault detection circuit indicates the presence of a fault within the associated complementary logic circuit.

Inventors: Durham; Christopher McCall (Austin, TX), Klim; Peter Juergen (Austin, TX), Walther; Ronald Gene (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G01R 31/30 (20060101); G01R 31/28 (20060101); H04L 001/08 ()

Expiration Date: 06/26/2018