Patent Number: 6,253,352

Title: Circuit for validating simulation models

Abstract: A circuit for measuring a propagation time of an edge of a signal between an input and an output of a logic cell. The circuit includes a plurality of logic cells of a first type that are electrically coupled in a series, and a plurality of multiplexers, each having a selection input, first and second data inputs, and an output. Each of the plurality of logic cells has a first input and an output, the output of each logic cell in the series being respectively electrically coupled to the first input of a next logic cell in the series. The output of a last logic cell in the series is electrically coupled to the first input of a first logic cell in the series to form a ring. The selection input of each multiplexer of the plurality of multiplexers is electrically coupled to the output of one logic cell in the series, with the output of each multiplexer being electrically coupled to the first input of the next logic cell in the series. The first and second data inputs of each multiplexer are set to different states. Embodiments of the present invention can be used to determine propagation times for each arc of a logic cell and to validate temporal models of logic cells in the context of a logic simulation with delay back annotation.

Inventors: Hanriat; Stephane (Saint Vincent de Mercuze, FR), Schoellkopf; Jean-Pierre (Grenoble, FR)

Assignee: STMicroelectronics S.A.

International Classification: G01R 31/30 (20060101); G01R 31/28 (20060101); G06F 017/50 (); H03H 011/26 ()

Expiration Date: 06/26/2018