Patent Number: 6,254,457

Title: Process for polishing wafers of integrated circuits

Abstract: A process for polishing, on a polishing machine and under defined polishing conditions, the external surface of at least one wafer of integrated circuits comprising a projecting feature covered over the entire surface of the wafer with an external layer of a material, consisting in calculating a main equivalent thickness equal to the main surface density of the projecting feature multiplied by the thickness of the latter; in polishing, under the defined polishing conditions, a reference wafer comprising an external layer of the material, having a uniform thickness and covering the surface of this reference wafer, so as to determine the rate of removal by the polishing machine corresponding to the ratio of the thickness removed to the polishing time elapsed; in calculating a polishing time equal to the ratio of the aforementioned equivalent thickness to the aforementioned rate of removal; in calculating a total equivalent thickness equal to the sum of the main equivalent thickness and of a complementary thickness of preset value; in calculating a polishing time equal to the ratio of this total-equivalent thickness to the aforementioned rate of removal; and in carrying out, under the polishing conditions, the polishing operation on at least one wafer to be polished for a duration which is equal to the aforementioned polishing time or which depends on this time.

Inventors: Perrin; Emmanuel (Biviers, FR), Robert; Frederic (Ambares, FR), Banvillet; Henri (Froges, FR), Liauzu; Luc (Grenoble, FR)

Assignee: STMicroelectronics, S.A.

International Classification: B24B 49/03 (20060101); B24B 49/02 (20060101); B24B 37/04 (20060101); H01L 21/02 (20060101); H01L 21/66 (20060101); H01L 21/3105 (20060101); H01L 21/321 (20060101); B24B 001/00 ()

Expiration Date: 07/03/2018