Patent Number: 6,254,676

Title: Method for manufacturing metal oxide semiconductor transistor having raised source/drain

Abstract: A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.

Inventors: Yang; Gwo-Shii (Hsinchu, TW), Huang; Michael W C (Taipei Hsien, TW), Huang; Chien Chao (Kaohsiung, TW), Chung; Hsien-Ta (Taichung, TW), Yew; Tri-Rung (Hsinchu Hsien, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 21/28 (20060101); H01L 21/20 (20060101); H01L 29/40 (20060101); H01L 29/417 (20060101); C30B 025/14 ()

Expiration Date: 07/03/2018