Patent Number: 6,254,718

Title: Combined CMP and plasma etching wafer flattening system

Abstract: A wafer flattening process designed to flatten the entire surface of the wafer to a higher precision by projecting the fall in the etching rate at the outer peripheral portion of the wafer and forming the outer peripheral portion of the wafer thinner in advance before plasma etching the entire surface of the wafer, a wafer flattening system, and a wafer flattened by the same. The wafer flattening system is provided with a CMP apparatus 1 and a plasma etching apparatus 2 are provided. The outer peripheral portion Wb of a wafer W held by a carrier 11 is polished thinner than an inside portion Wc of the wafer W by the CMP apparatus 1 having a platen 10 formed with a recessed surface. Specifically, it is polished so that the maximum thickness at the outer peripheral portion Wb of the wafer W becomes not more than the minimum thickness at the inside portion Wc. Suitably thereafter, the plasma etching apparatus 2 locally etches the surface Wa of the wafer W to obtain a wafer W with a high flatness without any projecting portion at the outer peripheral portion Wb.

Inventors: Tanaka; Chikai (Ayase, JP), Yanagisawa; Michihiko (Ayase, JP), Iida; Shinya (Ayase, JP), Horiike; Yasuhiro (Houya-shi, Tokyo, JP)

Assignee: SpeedFam Co., Ltd.

International Classification: B24B 37/04 (20060101); H01L 21/02 (20060101); H01L 21/306 (20060101); H05H 001/00 (); C23C 016/00 ()

Expiration Date: 07/03/2018