Patent Number: 6,255,125

Title: Method and apparatus for compensating for critical dimension variations in the production of a semiconductor wafer

Abstract: Prior to entering into manufacturing of a final production wafer, a series of test wafers are produced to analyze and test various structures. Each of the test wafers include a substrate, an insulating layer overlying the substrate, and a semi-conductive film layer formed over the insulating layer. The film layer is comprised of, for example, poly-silicon and has a predetermined thickness which substantially corresponds to the thickness of a film layer deposited on the final production wafer. The film layer is etched to form a desired pattern of structures and implanted with a dopant to diffuse dopant atoms thoughout. Thereafter, critical dimension measurements of the structures are taken preferably using electrical line width measurements techniques. Variations in critical dimension measurements taken from the test wafer as compared to desired predetermined line width measurements are compensated for prior to manufacturing the final production wafer so as to provide circuits with the desired electrical parameters.

Inventors: Schmidt; Regina T. (Milpitas, CA), Spence; Christopher A. (Sunnyvale, CA), Minvielle; Anna M. (San Jose, CA), Plat; Marina V. (San Jose, CA), Nguyen; Khanh B. (San Mateo, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 23/544 (20060101); H01L 021/66 ()

Expiration Date: 07/03/2018