Patent Number: 6,255,145

Title: Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product

Abstract: A process for forming a planar silicon-on-insulator (SOI) substrate comprising a patterned SOI region and a bulk region, wherein the substrate is free of transitional defects. The process comprises removing the transitional defects by creating a self-aligned trench adjacent the SOI region between the SOI region and the bulk region.

Inventors: Ajmera; Atul (Wappinger, NY), Sadana; Devendra K. (Pleasantville, NY), Schepis; Dominic J. (Wappingers Falls, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/266 (20060101); H01L 21/762 (20060101); H01L 21/308 (20060101); H01L 21/265 (20060101); H01L 021/00 (); H01L 021/84 (); H01L 021/76 (); H01L 021/31 (); H01L 021/469 ()

Expiration Date: 07/03/2018