Patent Number: 6,255,150

Title: Use of crystalline SiOx barriers for Si-based resonant tunneling diodes

Abstract: A method of forming a crystalline silicon well over a silicon oxide barrier layer, preferably for use in formation of a tunneling diode. A silicon substrate is provided of predetermined crystallographic orientation. A layer of crystallographic silicon oxide is formed over the silicon substrate and substantially matched to the crystallographic orientation of the silicon substrate. A layer of crystallographic silicon is formed over the silicon oxide layer substantially matched to the crystallographic orientation of the silicon oxide layer. The layer of silicon oxide is formed by the steps of placing the silicon substrate in a chamber having an oxygen ambient and heating the substrate to a temperature in the range of from about 650 to about 750 degrees C. at a pressure of from about 10.sup.-4 to about 10.sup.-7 until the silicon oxide layer has reached a predetermined thickness. In the case of a tunneling diode, the layer of silicon oxide has a thickness of from about 2 to about 8 monolayers and the layer of crystallographic silicon has a thickness of from about 2 to about 8 monolayers. A second layer of silicon oxide is provided on the layer of silicon remote from the layer of crystallographic silicon oxide. In the case of a silicon-on-insulator-type structure, the layer of crystallographic silicon oxide is from about 500 to about 2000 Angstroms and preferably 1000 Angstroms and the layer of silicon is from about 50 to about 1000 Angstroms and preferably 100 Angstroms.

Inventors: Wilk; Glen D. (Dallas, TX), Brar; Berinder P. S. (Plano, TX)

Assignee: Texas Instruments Incorporated

International Classification: H01L 29/66 (20060101); H01L 29/88 (20060101); H01L 021/337 (); H01L 021/00 (); H01L 021/331 (); H01L 029/06 (); H01L 031/032 ()

Expiration Date: 07/03/2018