Patent Number: 6,255,151

Title: Semiconductor integrated circuit device and method of manufacturing same

Abstract: A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

Inventors: Fukuda; Takuya (Kodaira, JP), Ohji; Yuzuru (Hinode-machi, JP), Kobayashi; Nobuyoshi (Kawagoe, JP)

Assignee: Hitachi, Ltd.

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/8242 (20060101); H01L 23/52 (20060101); H01L 21/3105 (20060101); H01L 23/532 (20060101); H01L 27/108 (20060101); H01L 021/336 (); H01L 021/823 ()

Expiration Date: 07/03/2018