Patent Number: 6,255,152

Title: Method of fabricating CMOS using Si-B layer to form source/drain extension junction

Abstract: A method of fabricating a CMOS transistor using Si--B layer to form a source/drain extension junction is disclosed. The fabrication includes the steps as follows; First, a p-type semiconductor substrate and an n-well region are provided. Afterwards, a shallow trench isolation (STI) is formed into the p-type semiconductor substrate and the n-well region, thereby forming a plurality of active regions therebetween. A channel is formed into the p-type semiconductor substrate and the n-well region. Then, a PMOSFET gate pattern and an NMOSFET gate pattern are formed over the p-type semiconductor substrate and the n-well region. A first defined photoresist layer is formed over the n-well region. Afterwards, the n.sup.- -type dopant is implanted into the p-type semiconductor substrate to form an n.sup.- -type lightly doped source/drain. Then the first defined photoresist layer is removed. A first dielectric layer is deposited over the p-type semiconductor substrate and the n-well region. A second defined photoresist layer is formed over the first dielectric layer. Afterwards, a portion of the first dielectric layer is firstly etched over the n-well region. Then an offset spacer is formed on the n-well region during a portion of the first dielectric layer etching step. Next, the second defined photoresist layer is removed. A Si--B (silicon-boron) layer is deposited over the n-well region and the first dielectric layer. The Si--B layer is oxidized to form a BSG layer, thereby firstly diffusing boron atoms into the n-well region to form a p.sup.- -type lightly doped source/drain. Afterwards, a second dielectric layer is deposited on the BSG layer. Next, a first BSG spacer and a second BSG spacer are formed, thereby etching a portion of the second dielectric layer, a portion of the BSG layer, and secondly etching a portion of the first dielectric layer. Afterwards, an n.sup.+ -type heavily doped source/drain is formed into the p-type semiconductor substrate. Next, a p.sup.+ -type heavily doped source/drain is formed into the n-well region. Finally, the first BSG spacer is annealed, thereby secondly diffusing boron atoms into the bottom region of the first BSG spacer to form a source/drain extension junction in a PMOSFET.

Inventors: Chen; Tung-Po (Taichung, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/70 (20060101); H01L 21/8238 (20060101); H01L 021/823 ()

Expiration Date: 07/03/2018