Patent Number: 6,255,153

Title: Method of manufacturing a semiconductor device

Abstract: The present invention is directed to a method of manufacturing a semiconductor device having a triple-well structure, comprising the steps of: forming a first pattern of a semiconductor substrate having a first N-well forming area, a R-well forming area, a second N-well forming area and a P-well forming area; forming a first layer within the substrate at a predetermining depth by implanting a N-type impurity ion using the first pattern as a mask; forming a bottom N-well within the substrate at a predetermined depth by implanting a N-type impurity ion using the first pattern as a mask; removing the first pattern; forming a second pattern on the substrate; forming a first lateral N-well and a second lateral N-well by implanting a N-type impurity ion using the second pattern as a mask, and portions of the first and second lateral N-wells overlap with opposite edge portions of the bottom N-well, thereby forming a N-well; removing the second pattern; forming a third pattern on the substrate; forming a second defect layer within the substrate at a predetermined depth by implanting a P-type impurity ion using the third pattern as a mask; forming a fourth pattern on the substrate; forming a R-well by implanting a P-type impurity ion using the fourth pattern as a mask; removing the fourth pattern; and performing rapid head treatment.

Inventors: Ryoo; Chang Woo (Kyungki-Do, KR)

Assignee: Hyundai Electronics Industries Co., Ltd.

International Classification: H01L 21/70 (20060101); H01L 21/8238 (20060101); H01L 27/085 (20060101); H01L 27/092 (20060101); H01L 021/823 ()

Expiration Date: 07/03/2018