Patent Number: 6,255,154

Title: Semiconductor device and method of manufacturing the same

Abstract: A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N.sup.- layer 22A) and deep in the vicinity of the drain region 5 (second N.sup.- layer 22B). This configuration contributes to boosting the withstand voltage and reducing the "on" resistance of the semiconductor device.

Inventors: Akaishi; Yumiko (Gunma, JP), Suzuki; Takuya (Saitama, JP), Mori; Shinya (Saitama, JP), Tsukada; Yuji (Gunma, JP), Watanabe; Yuichi (Gunma, JP), Kikuchi; Shuichi (Gunma, JP)

Assignee: Sanyo Electric Co., Ltd.

International Classification: H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 29/78 (20060101); H01L 21/266 (20060101); H01L 29/02 (20060101); H01L 29/66 (20060101); H01L 29/10 (20060101); H01L 021/823 ()

Expiration Date: 07/03/2018