Patent Number: 6,255,164

Title: EPROM cell structure and a method for forming the EPROM cell structure

Abstract: The present invention provides a cell structure of an electrically programmable read only memory (EPROM) which includes an EPROM gate structure, a source junction region, a drain junction region, a first dielectric layer, a self-aligned common source line, a self-aligned drain contact, a second dielectric layer, and a conductive line. The EPROM gate structure is on a portion of the substrate. The source junction region is in the substrate located on a first lateral side, namely the left side in the figure, of the EPROM gate structure. The drain junction region is in the substrate located on a second lateral side, namely the right side in the figure, of the EPROM gate structure. The first dielectric layer covers on top and sidewalls of the EPROM gate structure. The self-aligned common source line neighbors the first dielectric layer and is above the substrate on a portion of the source junction region. The self-aligned drain contact neighbors the first dielectric layer, and is above the substrate on a portion of the drain junction region. The second dielectric layer covers the first dielectric layer, the self-aligned common source line, and the self-aligned drain contact. The conductive line is on the second dielectric layer and communicates to the self-aligned drain contact.

Inventors: Liu; Chia-Chen (Hsinchu, TW), Wang; Ling-Sung (Hsinchu, TW)

Assignee: Worldwide Semiconductor Manufacturing Corp.

International Classification: H01L 21/70 (20060101); H01L 27/115 (20060101); H01L 21/8247 (20060101); H01L 021/824 ()

Expiration Date: 07/03/2018