Patent Number: 6,255,165

Title: Nitride plug to reduce gate edge lifting

Abstract: A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by etching a portion of the ends of the layer of tunnel oxide forming cavities, forming silicon nitride plugs in the cavities and forming a layer of oxide on the surface of the flash memory device wherein the silicon nitride plugs minimize gate edge lifting.

Inventors: Thurgate; Timothy (Sunnyvale, CA), Huster; Carl Robert (San Jose, CA), Sobek; Daniel (Portola Valley, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/336 (20060101); H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 29/49 (20060101); H01L 29/423 (20060101); H01L 29/40 (20060101); H01L 021/336 ()

Expiration Date: 07/03/2018