Patent Number: 6,255,166

Title: Nonvolatile memory cell, method of programming the same and nonvolatile memory array

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Inventors: Ogura; Seiki (Wappingers Falls, NY), Hayashi; Yutaka (Tsukuba, JP)

Assignee: Aalo LSI Design & Device Technology, Inc.

International Classification: H01L 21/336 (20060101); H01L 21/02 (20060101); H01L 21/28 (20060101); H01L 29/51 (20060101); H01L 29/40 (20060101); H01L 27/12 (20060101); H01L 29/66 (20060101); H01L 29/792 (20060101); G11C 16/04 (20060101); H01L 27/115 (20060101); H01L 021/336 ()

Expiration Date: 07/03/2018