Patent Number: 6,255,167

Title: Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gate

Abstract: A method of fabricating buried bit line flash EEROM cells with shallow trench floating gates for suppressing the short channel effect is disclosed. The method includes the following steps. First, a first polysilicon layer with conductive impurities and a nitride capping layer are sequentially formed on a silicon substrate. The nitride cap layer serves as an anti-reflection coating (ARC) layer for improving the resolution of lithography. Then a photo-mask pattern on the ARC layer is formed to define trench regions, an anisotropic etching is performed to etch away unmasked portions of the nitride cap layer through the first polysilicon layer and slightly recess the silicon substrate using the patterned mask as a mask. After removing the patterned mask, a thermal annealed process is performed to grow a polyoxide layer on the sidewall of the first polysilicon layer and an thin oxynitride layer on the surface of the recessed silicon substrate. In the meantime, the buried bit lines are formed where each bit line is a layer beneath the first polysilicon layer. The trenches are then refilled with a silicon layer. A planarization process then follows. Subsequently, an interpoly dielectric layer is formed. Finally, a second polysilicon layer is formed and pattered to define word lines.

Inventors: Wu; Shye-Lin (Hsinchu, TW)

Assignee: Texas Instruments - Acer Incorporated

International Classification: H01L 21/70 (20060101); H01L 27/115 (20060101); H01L 21/8247 (20060101); H01L 021/336 ()

Expiration Date: 07/03/2018