Patent Number: 6,255,168

Title: Method for manufacturing bit line and bit line contact

Abstract: A method for manufacturing a bit line and a bit line contact. A semiconductor substrate having a word line thereon is provided. Oxide spacers are formed on the sidewalls of the word line. A dielectric layer that covers the word line is formed over the entire substrate. A cap layer is next formed over the dielectric layer. The cap layer and the dielectric layer are patterned to form a trench in the dielectric layer. Silicon nitride spacers are formed on the sidewalls of the trench. In the subsequent step, the dielectric layer is etched down the trench to form a contact window that exposes a portion of the substrate. Polysilicon material is deposited into the contact window to form a polysilicon plug, and then metal silicide material is deposited into the trench above the plug to form a metal silicide layer.

Inventors: Gau; Jing-Horng (Hsinchu Hsien, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 21/8242 (20060101); H01L 021/336 ()

Expiration Date: 07/03/2018