Patent Number: 6,255,171

Title: Method of making dense SOI flash memory array structure

Abstract: A nonvolatile flash memory array having silicon device islands isolated from the substrate by an insulator. Each island comprises a split-gate transistor with a control gate and floating gate formed in the upper portion of the island, and source, drain and channel regions formed in a lower portion of the island. High array density is achieved by forming source and drain interconnects in the space between the islands. Also disclosed are processes for forming and programming such arrays.

Inventors: Noble; Wendell P. (Milton, VT)

Assignee: Micron Technology, Inc.

International Classification: H01L 21/70 (20060101); H01L 27/115 (20060101); H01L 27/12 (20060101); H01L 29/66 (20060101); H01L 21/8247 (20060101); H01L 29/788 (20060101); H01L 021/824 ()

Expiration Date: 07/03/2018